The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
if I talk to your previous boss, what he/she/they gonna say about you?
C++, SystemVerilog basics
Confidential. But related to system verilog and uvm.
Describe your previous projects and describe your contribution in them
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
Design verification lifecycle out of order scoreboard
Implement a state machine that detects modulo 5
design a vending machine from architecture to rtl..
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
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