2 lists which are connected. find the joint element
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Synchronous FIFO (based on the project), Memory design, C programming questions
2 rounds of Interview happened on the same day on call. Asked to code the monitor for a DUT. DUT was loaded with all the conditions with how it works which made it complex. SV constraint and some algorithm related questions were asked. All were of good quality.
static timing analysis
network theory
Define verilog ,systemverilog. Memory /cache
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
What will you do if you made a big mistake?
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