Verilog code for the clock divider
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Since the interview was for a hardware position, they asked more software related questions than I expected but were all easy
about gates basic concepts of c and java
What are some specific challenges you've faced in your current job, and how did you work through overcoming them?
Describe what a memory array looks like, what a sense amp generally does, and what an equilibration circuit does.
How do you construct a NOR gate only from NAND gates?
-Protocol Basics -Logic Gates -Design Projects [Verilog] -Verification Projects [SystemVerilog], UVM Fundamentals -C, C++ -OOP -Data Structures
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
How do you increase processor speed.
Basic Pipeline questions focused mainly on Branch Prediction and BTB
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