Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
Verification Engineer Interview Questions
3,649 verification engineer interview questions shared by candidates
Computer Architecture, Logic Puzzles, SystemVerilog, C, Algorithms,Assembly
Virtual functions, forks, verification basics, OOPs principle
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Basic question on UVM?
problem solving. debug a failure.
what factors of transistor affects the delay time
Basics of digital,. VLSI design etc
What is a hash table?
What is latency and throughput?
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