This was the main interview question. Design subroutine (pseduo code) that takes variable length of array whose element are in consecutive order but has one missing element. And minimum length of array should be 2. First and Last element can't be missing
Possible solution vectors to meet set up timing
FIFO design
How to implement not with nand/nor gates
muxs verilog
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Write the verilog code for a counter then change reset to asychronized.
Constraint randomization based question linking to AXI and memory filling
First of all, he asked about the project you have done. Then he asked me two problems related to probability and static. One is to calculate the pdf of the random variable which is function of a set of iid random variables, the other is to derive the MAP for given random variable with specific distribution.
1. How you will verify a block or any module that you designed? 2. Design divide by 3 counters with waveform? 3. Round robin arbitration logic? 4. Sequence detector (overlapping and nonoverlapping)? 5. Verilog code for synchronous and asynchronous flip-flop? 6. CMOS inverter circuit diagram and characteristics? 7. Ring inverter circuit and working? 8. Frequency of oscillations of ring oscillator? 9. Reset synchronizer circuit and working with waveform? 10. AHB Protocol working with waveforms? 11. Problem on Multi-cycle path? 12. Different ways of Synthesis optimization? 13. Identify the components that are consuming power in circuit? 14. How to save power in such power consuming block? 15. Dynamic power consumption formula? 16. Low power RTL coding styles?
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