Mainly asked about the research. What is my contribution to improve the overall performance of my design.
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
1. linked list 2. setup and hold problems 3. fsm for a particular sequence 4. stuck @ fault 5. circuit design for given waveform 6. verilog coding 7. project related questions 8. edge detector circuit 9. finding number of trailing zeroes in a factorial 10. reverse of a string 11. 3 black cap and 2 white cap puzzle 12. system verilog related questions 13. diff b/w blocking and non-blocking statements 14. basics should be strong
one question they asked is same as online test question and one verilog question and puzzle question.
some kind of high speed protocol and aske me to desgin in verilog
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
My previous experience, as well as a few mock examples related to verification and what my process would be
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Q.There was a discussion on mealy and moore machine.
The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
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