And gate using transmission gate
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
This was the main interview question. Design subroutine (pseduo code) that takes variable length of array whose element are in consecutive order but has one missing element. And minimum length of array should be 2. First and Last element can't be missing
Possible solution vectors to meet set up timing
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
They checked your resume and asked the questions related to your classes.
FIFO design
How to implement not with nand/nor gates
Questions on the resume. SV constructs, FIFO depth, STA questions
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
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