FIFO synchronized and asynchronized
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
How does Cadence Encounter solve setup time violations before CTS
ASIC flow, setup/hold, fix violation
clock divider / mealy vs moor fsm / through my resume project / setup time hold time
Explain the last project
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
Pipeline stuff
They asked a lot questions on pipeline design. Like how to optimize the overall ipc regarding branch? Is it possible to get branch resolved in decode stage?
Static Timing Analysis questions.
Viewing 791 - 800 interview questions