min and max timing violation
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Write the verilog of ROB on a paper.
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
One hot encoding, FSM divide by 3, Verilog coding.
Read after write sequence implementation
They asked about click domain crossing what do I know?
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
Delay analyst for latches and how to decrease the delay and clock period.
Design sequence detector with logic circuit diagram
How to debug a timing violation in the lab?
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