How we can integrate agents without them generating stimulus
Verification Specialist Interview Questions
3,655 verification specialist interview questions shared by candidates
During the interview, I was asked questions related to my experiences in the field. Setup hold, clock multiple. Specifically, discussions centered around the technical aspects of clock multiple, as well as an exploration of my work experiences and the responsibilities associated with my role.
7 questions total. One about arm products, 2 about coding in any programming language you want and 2 about coding in VHDL. Last question was if I Had any questions.
Is there anything else you would like to add?
Draw a block diagram of a simple processor and explain how a particular instruction will flow through it.
Explain Timing Diagram in VLSI
Assertions,SV OOPS, Comp Arch
Some verification related questions were asked?
RC circuit, Integrator differentiator, SystemVerilog, Digital circuits & STA
How to design an Accumulator. How to generate ramp signal in verilog. What are start and stop bits. Min. delay and Max. delay.
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