Mainly about FSM's and basics of programming languages, It is a plus if you understand the perspective of a HDL.
Verification Engineer Interview Questions
3,649 verification engineer interview questions shared by candidates
Implement Linked list - Verification components in a testbench - Modify classic 5 stage pipeline to accommodate SMT -
My experience was bad in 2 rounds otherwise good in other 3 rounds.
A general question that sees how is my verification thinking. Since I had no previous experience with verification, it took my a little while to understand what was asked.
Nothing was unexpected, very minimal behavioral questions. All the technical questions are regarding to computer architecture subjects.
tell about what you did in you last job, what you were responsible for
A function that generates and returns a randomized array comprising all integers from 1 to 100, with each integer appearing exactly once.
Basic question on UVM?
1. Talk about your work experiences and skills? 2. Mention two substantial technical challenges/great achievements and how you resolved them? 3. What is a singleton and how you create it and what are examples in UVM? 4. 10 CPU stages pipeline each of delay 10 ns, how long does it take to run 100 instructions? 5. Write a C code to know if the machine is big endian or little endian? 6. A Test failed and the designer came back and told you to change something to get the test work, you did that and the test case passed! Can you elaborate on this mentioning what the issue was and how to fix it. 8. you have numbers from 1 to 100 put in an array, you put the numbers in the array but the array length was less than 100, so it is missing a number. The array is shuffled and not sorted. Sketch an algorithm to get that number and mention its big O for performance and capacity? 9. You have an unsorted array, you want to find an 3 elements in the array in which their sum is equal to a specific number? 10. Write Verilog code for posedge/negedge detector? 11. Deep SystemVerilog assertions questions 12. Deep UVM questions (monitors with multiple analysis ports connections to scoreboard, how to collect input stimuli from the DUT (via monitor or sequence/sequencer, difference between p_sequencer/m_sequencer, UVM vertical and horizontal reuse, write code for TRANSLATION sequence, How to enable UVM acceleration in Emulation, etc.) 13. Deep SystemVerilog constrained random questions 14. Deep code optimizations, performance, capacity questions 15. Deep Emulation questions 16, Verify an arbiter using assertions 17. Sketch an algorithm to get the greatest K of an unsorted array. What is the BiG-O notation? 18. Write code to rotate a matrix. What is the BiG-O notation? 19. Power and clock optimizations questions. 20. Deep verification questions 21. UVM Register Layer Very deep questions
Strong focus on making sure Veriff and the candidate are on the same page in terms of values, future goals etc. (for example - relation to Veriff's mission)
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