Questions about myself and my work. Asked behavioral questions in between while explaining my past projects...
Verification Engineer Interview Questions
3,649 verification engineer interview questions shared by candidates
Example verification cases for a two-port memory block with address, data in, data out and a r/w enable.
asked about uvm and system verilog.few questions about sv constraints
Generate a clock divider using or gate
Technical questions: the same as LeetCode questions - Merge Sorted Array
Traversal of a binary tree to find given value
write a system verilog code to merge two sorted array and create a merged sorted array
Mainly riddles, about gates and other components
System Verilog and Formal Verification
Draw a FSM sequence detector
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