How to verify your design ？about testbench design ...
Verification Engineer Interview Questions
3,656 verification engineer interview questions shared by candidates
What's C++ STL
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
System verilog syntax
what is the most difficult person you met in your work? how did you handle that?
Questions were related to Digital design, RTL Verilog Coding, System Verilog and UVM
Quite unimaginative - Where do you see yourself in 5 years, what attracts you about the job etc. Google interview questions and the first ten that come up.
Configdb? Mailboxes etc
1]fabonassi series, 2]binary tree 3]sorting array without built in functions 4]probablities when randomizing 5] unique constraint.
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