how to balance the pipeline stage to achieve any specific time period?
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Implement Coverage for given scenario
C++ related Questions
UVM , system verilog and scoreboars related questions.
Write SV assertion for a req/ack protocol
Design a Flip Flop using transistors.
2nd phone interview: different methods for floating point multiplication.
Design scoreboard to compare dut and reference model.
Asked to explain the different BFM's i worked on and few questions on them.
Design a Cache, 32KB, 40 bit address, 64 Byte cache line, 4 way associative. How many bits are required to implement true LRU?
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