Murex,Semaphore,Deadlock memory management in brief.
Validation Engineer Interview Questions
2,442 validation engineer interview questions shared by candidates
Different debugging methods
A System under test scenario was described and asked several questions about how would you solle certain issues.
Several behavorial questions.
1. basics of cache coherency, cache architecture 2. Test plan scenario for different machines (ex: vending machine)
Do you have experience in Verilog?
Oops, identifying corner cases for specific designs, Computer Architecture concepts.
What is the purpose of cache in a CPU
They ask me about python, linux and c++
What technical skills do you have that are relevant to this role?
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