Self intro, basic definations in CTS and STA, low power design methodologies, local vs global skew, problems on sta
Rtl Design Engineer Interview Questions
212 rtl design engineer interview questions shared by candidates
Async fifo design and SDC contraints for it. Pulse synchronizer cross clock domains.
Lots of questions on OoO processor and Caches Learn more than what is given in your coursework
ASIC design processes, techniques, design processes
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
latch vs FF
Basics of digital K map based questions Verilog programing some logical ability questions
rtl basics questions digital design
Tell me about yourself.
About BTech project and basic digital Electronics
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