Phone screening 1. Questions about previous work experiences, digital circuit/layout design. 1:1 Technical interviews 1. RC circuits. Response to step input signal. 2. Transistor sizing for better setup/hold times. 3. Layout design of NAND3/NOR3 gates in different styles 4. Elmore delay of complex gates. 5. Standard cell library architecture choices and tradeoffs 6. Physical verification of standard cell libraries 7. DFM/DFD questions 8. Perl/Tcl and EDA tool related questions
Most questions were based on STA, timing and some based on PERL.
Explain Semi custom flow. STA. Layout verification related.
Basic pd questions, logical thinking
Flow of current in a layout ( given randomly by the interviewer)
Layout of an inverter, Verilog coding for a state machine, physical design flow
layout related questions, and generic cmos question
PNR flow, Sta, OCV, AOCV Internship experience based questions Physical verification and Routing
OCV related, Cross-talk related, timing analysis
was asked why 2 inverters are better that 1 buffer for fixing quality. and what the advantage of using 1 buffer that 2 inverters.
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