Working of SRAM where should we place the late arriving input in Nand gate
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
All the concepts of STA
What is pd flow and explain them with their input and outputs
Rd #1: > explain the complete RTL design of Async FIFO; with individual blocks - synchronizer, counter/ pointer, comparator, memory modules > what is meat-stability and how did you resolve it in FIFO; made use of gray code pointers > given a boolean logic, was asked to implement it using only NAND gates > write pseudo code for binary search, linear search Rd #2 > explain directed testing and random testing; explained with FIFO as an example > practical scenarios wrt SOC design - how feasible it is to turn on/ off a block, voltage/ freq scaling - which one to scale first while up/ down scaling > was asked to draw the block diag of PLL and explain individual components (from resume) > how to check if a design is functionally correct; functional coverage, code coverage, random testing for bugs Rd #3 > write truth table of 2 i/p nand gate, draw transistor level diag including sizing, explain the working wrt a particular case > write pseudo code in C/C++ or SV for given problem statement > verilog code of comparator Rd #4 > resume/ course oriented questions > interconnect delay, repeater insertion etc > questions on floor planning and place and route Rd #5 > signal integrity - cross talk, IR drop, EM, Antenna effect; ways to reduce it > from resume, asked to draw floor plan of one of my projects (SRAM memory bank)
Explain the different regions of operation of a MOSFET
Explain the 5-stage CPU pipeline
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
scripting, low power in vlsi, general digital vlsi question, depth questions in PnR flow
AOCV and POCV in detail
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
Viewing 461 - 470 interview questions