You have a device connected with a I2C bus. You send the data to the FIFO inside this device. How can you let the master know about FIFO overflow?
Fpga Engineer Interview Questions
681 fpga engineer interview questions shared by candidates
Questions related to CDC and Verilog/VHDL. one behavioral question. Questions from the resume.
Reverse an array in-place
How the FPGA works, what does it consists of? Types of communication busses and protocols (UART, SPI, I2C, PCI-express ...). Meta-stable condition. What is FIFO?
Bus protocols like SPI, ARM etc
We talked about my own project and the possibilities for its development.
When we need to partition our system on multiple fpgas?
Previous experience and coding part
What you have written in the resume, is it true? About my project on DSP: Have you worked on DSP algorithm? Was it on Xilinx FPGA or Altera?
OOP concept . like drawing problem. design object to do that.
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