Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
Digital Design Interview Questions
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Anything from coding to schematics to sta to low power to verification
What are the ways to reduce power consumption?
How to use muxes to implement an XOR gate?
What are some examples of scripts you have wrote, and give some scripting solutions to a problem, e.g. parsing timing reports.
FIFO setup/hold time state machine
Would you do anything differently if you could start you thesis again?
What did you do in your previous relevant experience
How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.
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