Question related to FSMs, which diagram describes the implementation better.
Digital Asic Design Engineer Interview Questions
47 digital asic design engineer interview questions shared by candidates
Introduction. Describe the working and the ranges of a transistor.
How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem. Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow Asked to design a 2 request arbiter.
I was asked to write the RTL code for an asynchronous receiver in Verilog
Had to fill in a truth table of a multiplexer
What it a flip flop and what does it do
design a trafffic light controller
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
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