Resume centric, cache coherence and consistence, rtl design and verification.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
about gates basic concepts of c and java
Basic UVM questions, monitor code and writing constraints.
Design Nand Gate using CMOS?
Design verification lifecycle out of order scoreboard
Implement a state machine that detects modulo 5
Basic stuff about Verification and assertions
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
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