Design, Test plan, SystemVerilog ......
Design Verification Interview Questions
1,115 design verification interview questions shared by candidates
how to resolve the issue with a malfunctioning vending machine with a pending deadline
Delayed assignment and delayed evaluation in Verilog
What is an isolation cell?
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
Verilog code for basic circuits
There was no tehnical interview for no experience engineer
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
SV, UVM, Driver sequencer handshake mechanism
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