Design Verification Engineer Interview Questions

1,115 design verification engineer interview questions shared by candidates

build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
avatar

Chip Verification/Design Engineer

Interviewed at Intel Corporation

3.9
May 30, 2025

build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.

Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
avatar

CPU Design Verification

Interviewed at Intel Corporation

3.9
Mar 18, 2016

Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.

45 mins phone interview: task vs function associative arrays packed vs unpacked scoreboard structures `uvm_do sequencer structure coverage: code vs functional functional cov: module and collector number of automatic bins for an int code coverage metrics uvm_object vs uvm_component concurrent vs immediate assertions 5hrs interview: reg model in uvm adapter and predictor scoreboard structure how to use some of the phases exercise on how to verify a DUT that gets data from 2 sensors list of quick questions on systemverilog how to verify req ack interfaces, also which assertions how to verify in a mixed signal enviroment find errors in given code (like missing "virtual" in parent/child sequences, or missing "automatic" in for loop with fork join_none) optimized way to generate Fibonacci's sequence recursive function to generate a given sequence shortest path algorithm: given starting point and destination point in a 2D matrix, get the shortest path from one to the other, including some non valid coordinates what kind of functional coverage I have done, how I've done scoreboards, some other questions about CV experiences
avatar

Design Verification Engineer

Interviewed at Apple

4.2
Jul 20, 2020

45 mins phone interview: task vs function associative arrays packed vs unpacked scoreboard structures `uvm_do sequencer structure coverage: code vs functional functional cov: module and collector number of automatic bins for an int code coverage metrics uvm_object vs uvm_component concurrent vs immediate assertions 5hrs interview: reg model in uvm adapter and predictor scoreboard structure how to use some of the phases exercise on how to verify a DUT that gets data from 2 sensors list of quick questions on systemverilog how to verify req ack interfaces, also which assertions how to verify in a mixed signal enviroment find errors in given code (like missing "virtual" in parent/child sequences, or missing "automatic" in for loop with fork join_none) optimized way to generate Fibonacci's sequence recursive function to generate a given sequence shortest path algorithm: given starting point and destination point in a 2D matrix, get the shortest path from one to the other, including some non valid coordinates what kind of functional coverage I have done, how I've done scoreboards, some other questions about CV experiences

Viewing 891 - 900 interview questions

Glassdoor has 1,115 interview questions and reports from Design verification engineer interviews. Prepare for your interview. Get hired. Love your job.