Design Verification Engineer Interview Questions

1,115 design verification engineer interview questions shared by candidates

If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?

Senior Design Verification Engineer

Interviewed at Microsoft

4★

Jun 18, 2015

What did you do in your last job?

Senior Design Verification Engineer

Interviewed at Microsoft

4★

Jun 18, 2015

What did you do in your last job?

Write verilog code for any flipflop. variations were also asked.

VLSI Design Verification Engineer

Interviewed at HCLTech

3.5★

Jan 8, 2026

Write verilog code for any flipflop. variations were also asked.

What's the different between CPU and microcontroller

Design Verification Engineer

Interviewed at UST

3.8★

Jan 19, 2026

What's the different between CPU and microcontroller

completely based on system verilog and digital design concepts

Design and Verification Engineer

Interviewed at Xilinx

4.2★

Feb 24, 2017

completely based on system verilog and digital design concepts

Talk about resume, explain the detail. ask some related questions on the project.

Design Verification Engineer

Interviewed at Shanghai Zhaoxin Semiconductor

3.3★

Nov 13, 2020

Talk about resume, explain the detail. ask some related questions on the project.

Basics of UVM and SV

ASIC Design Verification Engineer

Interviewed at Green IP Core

Feb 15, 2021

Basics of UVM and SV

Grilled on my current work, System Verilog basics, UVM in depth, Comp Arch questions like Cache coherency.

Verification Design Engineer

Interviewed at Samsung Austin Semiconductor

3.4★

Nov 4, 2017

Grilled on my current work, System Verilog basics, UVM in depth, Comp Arch questions like Cache coherency.

Should be ready to write some logic (C/Verilog/System Verilog) on the spot

Verification Design Engineer

Interviewed at Eximius Design

3.6★

Feb 12, 2020

Should be ready to write some logic (C/Verilog/System Verilog) on the spot

Energy - cost - time trade offs

Verification Design Engineer

Interviewed at Qorvo

3.5★

Feb 9, 2020

Energy - cost - time trade offs

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