I was asked to write system verilog constraints for a variety of random stimulus needs.
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Register renaming
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
Test cases for a 2 input, 2bit adder.
What is the difference between blocking and non-blocking assignments?
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
Questions on C++, Perl, System Verilog.
Can you talk about your past experiences?
General questions about C, pipelining, caching, hazards and more C.
Functional coverage vs. Code Coverage
Viewing 701 - 710 interview questions