What is the probability that we going to have a hit on a cache if the TAG is XXX on a 32 or 64 bit ?
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
1. SV constraint 2. UVM 3. Resume review
Questions on analog designs and filters. Questions on digital designs. Questions on SystemVerilog and Verilog.
Digital design basics, SV, UVM, SVA
Generate clock using always and forever in verilog
Describe how CAM (content addressable memory) works.
Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["
Tell me about yourself and then questions on verilog
write constraint for memory system
Resume - past experiences and projects
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