FIbonacci series
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
how to design a FSM using switch-case / shift register
Verification plan of any given design, assertions, what is coverage?
* Have you used UVM? * What is your knowledge level of SystemVerilog?
Do you have prior experience with UVM and System Verilog
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
- about SV, FIFO design, arbiter design
Draw a state machine that accepts the sequence 101
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