state machines, FIFOs sync and non-sync, clock domain crossing, meta stability, buses
Design Engineer Trainee Interview Questions
31,088 design engineer trainee interview questions shared by candidates
Write the latch verilog code
Design a FSM for outputting x/3 without the remainder.
about projects , global routing
Some flip flop questions, logic design questions, and static timing questions
Asked about Cache math
question will be on structural design related and few apptitude
difference between setup and hold time
about dff and clocks
In addition to technical questions there is alos behavioral questions asked. One example is "tell me about a time when you had to do something different from what the conventional approach suggested".
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