Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
explain briefly about the inverter and its characteristics
Typical timing probs (fix hold time and setup time violations, power saving techniques, jitter, skew) Some simple comp arch (5 stage pipeline, hazards and how to fix them, VM) HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew and explain in detail.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Given an array A[] and a number x, check for pair in A[] with sum as x
How do you handle arguments
Mostly questions on solidwork and they are expecting to good to have experience on solidwork with your current organisation.
Question on your current and past experience mostly.
Why should we pick you instead of others
Are you comfortable working out of your own vehicle.
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