1. Design Synchronous counter and walk me through the process. 2. Design 2 to 1 multiplexer using transmission gates. 3. Gave a circuit and asked about Setup time and Hold time and violations, if any.
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Transistor properties, Inverter, logic design.
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Using mux to realise various combinational gates
Synchronous and Asynchronous D implementation, Ram Rom Cache
Questions were on STA, FSM, backend etc.
How to design a clock divider without counters
What are Setup and Hold Times? Can you propose the optimal clock frequency for the following circuit?( A circuit with setup, hold and delays is given)
Solve RC CIRCUITS - basic to moderate level 1/2 little hard (2nd order)
How many people are flying right now?
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