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Design Digital Interview Questions
823 design digital interview questions shared by candidates
Was asked about basic protocols for PCIE. Basic questions on CDC. Types of violations that the CDC tools complain - eg: no_sync, combi logic before double sync, multi bit double syncing, re-convergence etc. Code async reset FF and sync reset FF. What are the dis/advantages of one over the other.
What is the difference between a Mealy and Moore FSM?
For aptitude, the interviewer asked me roughly how many trees I pass by from my house to the campus.
Lots of questions about pmos and nmos (how to build nand gates, inverters), etc, how a pll works, how different things affect the output, transmission lines (parasitics, series vs parallel etc), flip flops, latches, op amps (designing lots of different op amps and discussing their rules)
See interview process, the questions are listed in there
What I excepted from the job, technically speaking.
Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
Anything from coding to schematics to sta to low power to verification
What are the ways to reduce power consumption?
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