Garage door opener in verilog
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
nothing in particular
round robin algorithm, scheduling? state diagram?
Black box CRC circuit checking...
FIFO synchronized and asynchronized
How does Cadence Encounter solve setup time violations before CTS
ASIC flow, setup/hold, fix violation
clock divider / mealy vs moor fsm / through my resume project / setup time hold time
Explain the last project
Viewing 1281 - 1290 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Vlsi Design EngineerVlsi EngineerAsic Physical Design EngineerSenior Asic Design EngineerSoc Design EngineerRtl Design EngineerHardware Asic Design EngineerPhysical Design EngineerSenior Dft-ingenieurHardware Engineering ManagerHardware Asic Ontwerp IngenieurSenior Fpga Design EngineerFpga Design EngineerFpga Development EngineerSenior Hardware Design EngineerSenior Asic Fpga Design EngineerAsic Design Verification Engineer