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Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
1. Some simple random stimulus with specified constraints
related to RTL and UVM
Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Provided a waveform and asked to design a circuit for that.
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Detect that N numbers have arrived based on a control signal. Flag the average of all the N numbers once the N-numbers have arrived.
Optimize a digital circuit for power and for delay, difference between a shift register and a FIFO, priotity MUXing, logic question
Clocking and timing analysis about a register circuit.
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