All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Asic Design Verification Engineer Interview Questions
106 asic design verification engineer interview questions shared by candidates
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What's your name , is it [name] ?
They mostly concentrated on sv , uvm
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Debugging scenarios of latest project
What is Setup time and Hold Time? Verilog and C syntax related Questions. Questions of Digital Electronics
Call uvm_agent function from uvm_sequence to display "hello world"
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