Asked me about my courses at my university. Did you take any verification course. Which university you did in your bachelors in. Why do you like verification?
Asic Design Verification Engineer Interview Questions
106 asic design verification engineer interview questions shared by candidates
Questions on constraints and assertions
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
There were no out of the box questions.
What will affect power consumption?
They gave a class - asked to create it's objects and send out random objects in a function.
questions on digital electronics and verilog
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
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