Phone interview questions: 1. How do you achieve run time polymorphism? 2. What is meant by casting of objects?
Asic Design Verification Engineer Interview Questions
106 asic design verification engineer interview questions shared by candidates
Explain the UVM Sequencer driver communication
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
Write a verilog code for dual Port ram using 2 single port ram
What is handshake mechanism in uvm and explain how to override
The interviewer asked some verification questions - those were nice; but then he also asked a software (i.e "cracking the coding interview") type of question. I'm not a Software Engineer
AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
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