asynchronize fifo coding
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
1. Explain Fork Join, None with example? 2. Calculating FIFO Depth? 3. Many Questions on UVM.. & System Verilog
Given a block diagram, how would you connect everything internally to make it work?
What greek philosopher didn't write any of his works?
Basics of CMOS at transistor level.
How to realize a communication between different time domain?
what are sorts and tell different types of sorts ?
What are setup and hold time violations ? Showed me timing diagrams and asked me to explain the setup and hold times.
setup/hold timing
They ask all basic questions about VLSI
Viewing 701 - 710 interview questions