Clock domain crossings and reset domain crossings
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
questions on digital electronics and verilog
What is your experience with random constrained stimulus?
Basic Design questions on Flip Flops, Digital VLSI Design, Setup and Hold time violations. Interviews mostly judge your confidence and that you know the stuff you are talking about
Basics of UVM and SV
4. How always @ (posedge reset or negedge clk) synthesized
2. CDC and Types of synchronizer
Problem solving approach Core VLSI concepts
Genral questions 1 setup time hold time 2 verilog basics verilog caculating (a+b)/2 or (a+b+c+d)/4, how to round 3 what 's the use of arbitrary 4 vending machine state machine 5 architecture pipeline
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