False paths and Multiple cycle path examples.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
How to design an 64 bit adder if only given a 32 bit adder. After you design it, you will be asked how to verify it. The verification maybe related to SystemVerilog.
how to avoid overflow in FIFO design; design a FSM for bit string detect
VLSI, Device Physics, Cadence, Verilog and C Programming.
State machine, gate level design
Introduce your education background
electronics the technical questions like find the output of flip-flops find the output at a specific clock cycle combinations of flip flops and mux simplifications of gates transmission gate problem basic electronics like temperature were given flipflops and interview time played a dominant role in the first round
From basics to complex fundamentals
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Visually Identify between combinational and squential elements
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