How to design an 64 bit adder if only given a 32 bit adder. After you design it, you will be asked how to verify it. The verification maybe related to SystemVerilog.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
how to avoid overflow in FIFO design; design a FSM for bit string detect
all about resume, STA, DFT, Pipelining
There were no out of the box questions.
calculate set up , hold in terms of some 10 parameters.
1. Reverse the contents in an array in C
Why you do clk gating in your design
How to determine which register you want to gate in netlist ?
How often do you use the digital programming software?
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