Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
How to turn a 40% duty cycle clock signal to a half frequency signal with 50% duty cycle.
SRAM Design and follow up questions
how would you code an adder in verilog
Asked about the OA (1st round), like explain your answers..
What did you do in the past, how to implement low power design, how to build CTS, how to do STA
Nothing really, some pros/cons of different physical verification tools, how to filter through 100k+ errors, how to solve chip level LVS issues. Should be easy for experience engineers to answer.
what I did?
Bus protocols like SPI, ARM etc
Can't remember.
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