I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
The second was about state machine, how to output true for every two consecutive 1s.
Trick question on FIFOs.
Difference Between Associative array and Dynamic Arrya
What are you currently working on?
Have you built a library before
Computer architecture, cache coherence, CPU design, pipelining
Design an inverter using digital logic Triangle leetcode Q
Logic gates (inverter using mux), FSM sequence detector, digital design
how to use UVM events and UVM pool
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