Basic c coding questions and digital electeonics questions
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
how to mimimize setup time and hold time violation?
4 bit counter
1. Verilog question: given 1 bit data, clock and 1 output. Every clock rise- the data is sampled. You need to turn on the output bit every time there is a sequence of 4 bits -1101.
What would be the effect of adding ESD protection to an output driver.
UPF file in low power design
Describe a scenario when you had to work in a group, or manage project, or resolve conflict, etc
How to do CDC, why gray codes
Draw a inverter in logic form and in CMOS configuration. And explain the physics behind it.
What is polymorphism?
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