JLR interview questions

The DV (Design Verification) engineer interview process typically involves a combination of technical and behavioral rounds. Candidates are tested on knowledge of digital design, verification methodologies (like SystemVerilog, UVM), debugging skills, and problem-solving ability. Expect coding challenges, conceptual questions, and discussions on past projects and teamwork.

The interview was with the hiring manager and a vital stakeholder connected with the role. I was asked about my experience, various projects I had completed in the past, and my ability to make use of some software's related to project management